With AMD CPU market share down in the pits, everyone is looking towards Zen to give Intel some competition in the high-end segment. Even with DX12 reducing the need for a strong single threaded CPU, there is nothing like a good architecture that can compete with Intel, especially in non-gaming applications. In their latest patch dealing with Zen, AMD has revealed some more details about the inner workings of their upcoming CPUs, with the focus on the caches.
First off, Zen will introduce a new L0 cache, meaning that there will actually be 4 levels of cache. The L0 cache is a uOp cache, something Intel added back with Sandy Bridge. Paired with the uOp buffer, this will help reduce power consumption when running loops or if something needs to be re-executed quickly. Intel’s cache is 1.5KB so we can probably expect AMD to follow similarly as speed is more important than size.
Next up are changes to the L1 Instruction and Data caches. The L1 I$ will be 32KB, a drop compared to Steamroller/Excavator and K10 but back to the same size as Piledriver. The L1 D$ is also expected to be 32KB, a doubling over Steamroller and the same that of Excavator though still lower than K10. The reduced L1 I$ may be offset by the new uOp cache. The L2 may remain the same since the days of K10, with 512KB. This may be a problem if the rumoured inclusive cache design is used as 2304of the rumoured 8MB of L3 will be used in duplicating data. Having everything duplicated in L3 may make for better core-sharing and multi-threaded performance but limits everything to near L3 speeds for cache writes.
Overall, the cache changes suggest a move to ensure faster, rather than large caches. The increases to the caches also point to the focus on keeping the cores fed as well as high-speed cores with a long pipeline. This all helps with the 40%+ IPC improvement AMD is hoping for with Zen. Overall, Zen is looking to be a very wide and balanced design, borrowing from Intel and K10 but without any of the baggage of the past.
