AMD Teases Vega Architectural Upgrades

Ahead of the new Vega Architecture Preview, AMD has dropped some more hints about their upcoming GPUs. Along with the new countdown timer on the teaser page, AMD has also uploaded a word cloud with some key tags. A quick look at these keywords tells us a whole lot of information about Vega, especially once we consider what has already been revealed and leaked thus far.

First off we have the 8x capacity/stack which is a reference to HBM2. Compared to HBM, HBM2 features 8 times the DRAM density per stack, allowing for fewer stacks or higher capacities beyond the 4GB limit Fiji faced. This ties into the 2x Bandwidth per Pin which is also HBM2 relative to HBM, allowing for narrower memory busses to hit the same bandwidth. Combined, these two new features should allow larger VRAM capacities at an increased bandwidth at a lower cost. The 2x Peak Throughput per Clock could be a reference to HBM2 bandwidth as well.

In terms of Vega specific features, there are a couple. First, we have the High Bandwidth Cache and High Bandwidth Cache Controller. This means Vega is likely getting a new improved cache layout with improved bandwidth and latency compared to Polaris. The improved bandwidth will help feed the new Next Generation Computer Engine and Vega NCU which is likely an improved CU (Compute Unit) over GCN 4.

Lastly, there are also a few other keywords that are bit too vague to pick out specifics but appear interesting. The 512 TB of Virtual Address Space is likely to be a boon for compute users while the Next Generation Pixel Engine, Primitive Shaders, and Draw Stream Binning Rasterizer hold a lot of potential depending on what they actually turn out to be. It will be interesting to see AMD has in store for us in just a little over 2 days.