AMD Laying Groundwork for Zen 2
Sometime in the near future, AMD will be launching their new Zen 2 CPUs. The new designs build on the great work that AMD has already done for Zen and Zen+. With a projected 13% IPC increase, performance is definitely up. Along with base IPC improvements, we can expect new instruction set support. To prepare for Zen 2, the company is already starting to patch in support. The latest is the GNU compiler which is getting a few new instructions.
The GNU compiler is currently about to get its 9.0 release. Due to the new release, AMD is submitting their first Zen 2 patch. Furthermore, we can expect more patches to come with 9.1 and onwards. The patch contains the CPU identifier for Zen 2. It also provides support for a number of new instructions. These are Cache Line Write Back (CLWB), Read Processor ID (RDPID), and Write Back and Do Not Invalidate Cache (WBNOINVD).
Zen 2 Expected to Offer 13% IPC Increase
Along with these basic instructions, we can expect some new ones as well. Furthermore, one thing that AMD will want to do is catch up to Intel on instruction parity. Due to starting as the underdog, Intel does have a lead in this area. However, as a result of various delays, AMD has a chance to catch up. Some instructions that AMD might want to add are the usual basics such as AVX 2 and perhaps AVX512. Finally, FMA4 may also make an appearance along with Spectre hardware fixes.
So far, from what we know, the company is working on iterating on Zen. For at least until Zen 5, the basic architecture will remain largely the same. However, the implementation may vary widely with changes perhaps to the MCM. While we won’t be seeing massive 50% IPC increases in the near future, AMD should be able to keep up with Intel. The next big jump we will see will likely be due to either new substrates instead of silicon or a reimaging of computing ala Quantum Computing.
