ARM Unviels DynamIQ Dynamic big.LITTLE CPU Clusters

Over the past decade, ARM has established a stranglehold on the mobile CPU market. Starting from the simple single core designs, the CPUs have grown to dual, quad and even octa-core configurations. To make better use of higher core counts, ARM introduced the big.LITTLE designs with 2 core clusters, with one optimized for power efficiency and the other for performance. With their new DynamIQ, the big.LITTLE concept is moving to it’s next logical step.

DynamIQ is mainly focused on heterogeneous scalability. Right now, big.LITTLE uses 2 or 3 different core clusters which has its bonuses and drawbacks. With DynamIQ, there will only be a single cluster of cores but the cores within the cluster can all be different. Not only can different clock speeds be utilized but also architectural differences and even the cache sizes. For instance, a single cluster could feature a single A73 high-performance core, 2 A57 performance cores, 4 A53 low power cores and a single M-series slumber core. This allows for an even greater mix in computing power.

Instead of having to migrate data between clusters, the threads stay within the same cluster, sharing the cache via a new data fabric. This should hopefully mitigate the transfer performance penalty between high and low-performance cores and allow more efficiency gains. The new data fabric is also set to allow redundancy, with multiple clusters performing the same work. This not only allows clusters to fail without compromising the system but also allows results to be cross-referenced to find errors. Similar systems are used for autonomous train control computers so the likely application will be with self-driving cars.